1. Field of the Invention
The present invention relates generally to a semiconductor device which has enhanced withstand voltage property. More particularly, the invention relates to a structure of a semiconductor device having PN junction with improved withstand voltage.
2. Description of the Background Art
For semiconductor devices, such as semiconductor diode, gate turn-OFF thyristor and sop forth, it is essential to weaken electric field of surface of PN junction so as to maintain withstand voltage at high level and to prevent the device from causing avalanche at relatively low voltage. In order to weaken the electric field at the PN junction surface, Bevel structure is generally employed by providing taper for the surface to which the end of the junction is exposed. There is two way of providing Bevel structure for the surface. One way is to form a positive Bevel structure, in which cross section is gradually increased from the upper high resistant layer which has relatively low concentration of dopped N-type impurity to the lower low resistance layer which has relatively high concentration of dopped p-type impurity. The other way is to form a negative Bevel structure, in which cross section is gradually decreased from the upper high resistant layer to the lower low resistant layer.
In the recent years, there have been proposed improved constructions of semiconductor devices which has lower ON voltage. Such recently proposed semiconductor devices has architecture of PN.sup.- N.sup.+, P.sup.+ NN.sup.+, PIN, P.gamma.N and so forth. In the PN.sup.- N.sup.+ architecture, N-type high resistant layer is separated into N.sup.- layer which has low N-type impurity concentration and N.sup.+ layer which has high N-type impurity concentration. The PN.sup.- N.sub.+ architecture has been advantageously employed in the modern semiconductor devices because it achieves lower. ON voltage by reducing width of N.sup.- N.sup.+ layer by terminating depletion region with the N.sup.+ layer
For such modernized semiconductor devices, the positive and negative Bevel structures are not effective for reducing strength of the surface electric field. Therefore, such conventionally known Bevel structure is not applicable of the modernized semiconductor devices such as that set forth above. Namely, when the positive Bevel structure is employed for PN.sup.- N.sup.+ architecture semiconductor device, electric field concentrates to the N.sup.+ layer to cause lowering of the withstand voltage. For improving this, various attempts have been made. In one approach, different taper angle of negative Bevel structure is provided. In the prior proposed architecture, P and N.sup.- layers are provided at smaller taper angle with respect to the vertical axis than that of the N.sup.+ layer. On the other hand, it is possible to provide positive and negative Bevel respectively for P layer and N.sup.+ layer. In either case, configuration of the semiconductor devices become complete to cause difficult in processing to form desired Bevels. Also, the complicate configuration causes difficulty in forming dust proof and/or shielding layer with polyimide or silicon rubber. In addition, such prior proposed structure requires process of relatively wide area to cause reduction of the effective area.